This invention relates to a method of controlling a logical simulation of a logic circuit in response to an input stimulation signal. It is to be noted here that such a logical simulation is carried out in a simulator, namely, a computer by the use of the logic circuit logically formed therein and that a logic circuit may be distinguished from an actual or hardware logic circuit for convenience of description.
A logical simulation of the type described is used to assure operation of logical behavior of a hardware logic circuit or to evaluate the quality of a test pattern for testing a manufactured hardware logic circuit. The logical simulation may be carried out by the use of software, firmware, or hardware.
In general, the logical simulation is controlled by a control method which is applicable to any other logical simulation. As will later be described with reference to one figure of the accompanying drawing, such a control method is intended to put the logic circuit into operation in a manner similar to the hardware logic circuit. In other words, operation of the hardware logic circuit is faithfully reproduced or simulated by the logical simulation of the logic circuit.
In an article contributed by Funatsu et al to the Proceedings of 12th Design Automation Conference, page 114--page 122 (June 1975), and entitled "Test Generation Systems in Japan", a proposal is made about a simulation method of simulating a hardware logic circuit by making a plurality of sequential circuits, such as registers or flip flops, form a scan-path or a shift register string. The simulating method facilitates testing the hardware logic circuit because formation of the shift register string serves to readily load the sequential circuits with logic signals and to readily observe internal states of the sequential circuits. Thus, the above-mentioned hardware logic circuit will be called a hardware logic circuit of a scan-path type.
When the above-described control method is used to control a logical simulation of a specific logic circuit related to the scan-path type of the hardware logic circuit, a serial shift operation should inevitably be controlled to load a shift register string with a sequence of logic signals in synchronism with a sequence of clock signals and to read internal states out of the shift register string like in the hardware logic circuit. A long time is wasted by such a serial shift operation.
It is accordingly difficult to carry out, by the use of the above-mentioned control method, the logical simulation of the scan-path type of the hardware logic circuit at a high speed.